FIG. 1 is a block diagram showing an example of a personal computer 1 having a network card for executing a DMA (Direct Memory Access) transfer using a descriptor.
As shown in FIG. 1, a CPU (Central Processing Unit) 11 is connected to a ROM (Read Only Memory) 12 and a RAM (Random Access Memory) 13 through a bus 14. The CPU 11 executes various processings according to a program stored to the ROM 12 or a program recorded to a recording unit 18.
For example, the CPU 11 causes a descriptor region 31 (to be described later) of the RAM 13 to store the address, the packet size (length), and the like of the packet region 32 of the RAM 13, to which a packet as a target of DMA transfer is stored, as a descriptor, thereby a network card 19 DMA transfers the packet.
Further, CPU 11 executes an interrupt processing by reading out an interrupt status showing an cause of generation (status) of an interrupt signal stored to the network card 19 in response to the interrupt signal supplied from the network card 19 and executing an interrupt status processing corresponding to the interrupt status.
RAM 13 is composed of a descriptor region 31 in which the descriptor is stored, a packet region 32 in which the packet as the target of the DMA transfer is stored, and the like.
An input/output interface 15 is connected to the CPU 11 through the bus 14. An input unit 16 composed of a keyboard, a mouse, and the like and an output unit 17 composed of a CRT (Cathode Ray Tube) display and the like are connected to the input/output interface 15. Then, CPU 11 executes various processings in response to an instruction input from the input unit 16. Then, the CPU 11 outputs an image, audio, and the like obtained from a result of a processing to the output unit 17.
The recording unit 18 connected to the input/output interface 15 is composed of, for example, hard disc and the like and records the program to be executed by the CPU 11 and various types of data. The network card 19 executes a DMA transfer. Specifically, the network card 19 reads out a packet stored to the packet region 32 of the RAM 13 based on the descriptor stored to the descriptor region 31 of the RAM 13 and transmits the packet to other apparatus through a not shown network. Further, the network card 19 receives a packet from the other apparatus through the not shown network and causes the packet region 32 of the RAM 13 to store the packet based on the descriptor.
Further, the network card 19 generates an interrupt signal and supplies it to the CPU 11 as well as sets an interrupt status and stores it.
When a removable media 21 such as a magnetic disc, an optical disc, an optomagnetic disc, a semiconductor memory, or the like is mounted on the drive 20 connected to the input/output interface 15, the drive 20 drives it and obtains the program, data, and the like recorded thereto. The obtained program and data are transferred and record to the recording unit 18 when necessary.
FIG. 2 is a block diagram showing an example of a functional arrangement of the network card 19 of FIG. 1.
The network card 19 of FIG. 2 is composed of a DMA transfer unit 51, a packet communication unit 52, an interrupt generation unit 53, and an interrupt status holding unit.
The DMA transfer unit 51 controls the DMA transfer. Specifically, the DMA transfer unit 51 reads out the descriptor from the descriptor region 31 (FIG. 1) in response to a DMA transfer request supplied from the CPU 11. Then, the DMA transfer unit 51 reads out a packet as a target of DMA transfer from the packet region 32 based on the descriptor and supplies it to the packet communication unit 52 or stores a packet supplied from the packet communication unit 52 to the packet region 32. Further, the DMA transfer unit 51 supplies the status information showing the status of processing (for example, transmission/reception completion state of a packet, an error state of transmission/reception, and the like) executed by and supplied from the packet communication unit 52 to the interrupt generation unit 53.
The packet communication unit 52 transmits the packet from the DMA transfer unit 51 to other apparatus through the not shown network. The packet communication unit 52 receives the packet from the other apparatus through the not shown network and supplies it to the DMA transfer unit 51. Further, the packet communication unit 52 supplies the status information to the DMA transfer unit 51.
The interrupt generation unit 53 generates an interrupt signal in response to the status information from the DMA transfer unit 51 and supplies it to the CPU 11. Further, the interrupt generation unit 53 sets an interrupt status in response to the status information, supplies the interrupt status to the interrupt status holding unit 54, and causes the interrupt status holding unit 54 to store it.
The interrupt status holding unit 54 holds the interrupt status from the interrupt generation unit 53. The interrupt status holding unit 54 clears (deletes) the interrupt status in response to a request from the CPU 11.
Next, an interrupt generation processing executed by the personal computer 1 will be explained referring to FIG. 3,
At step S11, the interrupt generation unit 53 of the network card 19 generates an interrupt signal in response to the status information from the DMA transfer unit 51 and notifies (transmits) the interrupt signal to the CPU 11, and then a process goes to step S12.
At step S1, the CPU 11 receives the interrupt signal from the interrupt generation unit 53 and the process goes to step S2. At step S2, the CPU 11 requests the network card 19 to read out the interrupt status, and the process goes to step S3.
At step S12, the interrupt status holding unit 54 of the network card 19 receives the request for reading out the interrupt status from the CPU 11, and the process goes to step S13. At step S13, the interrupt status holding unit 54 notifies (transmits) the interrupt status held thereby at the time in response to the request for reading out the interrupt status, and the process goes to step S14.
At step S3, the CPU 11 receives the interrupt status from the interrupt status holding unit 54, and the process goes to step S4. At step S4, the CPU 11 executes an interrupt status processing corresponding to the interrupt status.
When, for example, the interrupt status shows the completion of transmission of a packet as a target of DMA transfer executed by the packet communication unit 52, the CPU 11 releases the packet region 32, to which the transmission-completed packet is stored, as an interrupt status processing. That is, the CPU 11 deletes the transmission-completed packet stored to the packet region 32.
After the processing at step S4, the process goes to step S5, at which the CPU 11 requests the network card 19 to clear the interrupt status held to the interrupt status holding unit 54, thereby the processing is finished. As described above, the CPU 11 executes the processings from steps S2 to S5 as the interrupt processing in response to the interrupt signal supplied from the interrupt generation unit 53 at step S1 and finishes the processing.
At step S14, the interrupt status holding unit 54 of the network card 19 receives a request for clearing the interrupt status from the CPU 11 and clears the interrupt status in response to the request. That is, the interrupt status holding unit 54 clears the respective bits of the held interrupt status (signal).
Incidentally, various methods are conventionally proposed in an apparatus for executing an interrupt processing to reduce a load of an interrupt notification processing. For example, there is an interrupt processing system having an interrupt aggregation means interposed between an interrupt generation device and an interrupt processing device to prevent multiple interrupt (refer to, for example, Patent Document 1).
Further, there is a data transfer system for reducing the number of times of notification in such a manner that when a DMA transfer is completed, a DMA controller of an external I/F (interface) equipment updates only the status of an interrupt signal stored to a status register in the external I/F equipment without generating an interrupt signal to a CPU, and the CPU refers to the status stored to the status register in response to a timer interrupt generated at each predetermined time (refer to, for example, Patent Document 2).
[Patent Document 1] Specification of Japanese Patent No. 3549703
[Patent Document 2] Japanese Unexamined Patent Application Publication No. 11-212904